Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, thereby providing a high degree of integration. DRAM, however, requires constant refreshing, which limits use of DRAM to computer main memory. An SRAM memory cell, by contrast, is bi-stable, meaning that it can maintain its state indefinitely, so long as an adequate power is supplied. SRAM also supports high speed operation, with lower power dissipation, which is useful for computer cache memory.
One example of an SRAM memory cell is a six transistor (6T) SRAM memory cell that includes six metal-oxide-semiconductor (MOS) transistors. As processes for fabricating MOS devices migrate to nanometer technologies, the use of conventional 6T SRAM cells within processor cache memories prohibits compliance with performance requirements. To meet these performance requirements, eight transistor (8T) SRAM cells are being used in place of the 6T SRAM cells. Use of an 8T SRAM cell may enable independent sizing of the devices on the read and write ports of the memory cell for supporting a lower minimum write voltage (Vmin), while enabling a high performance read operation.
However, process variations in nanometer technology on read port devices for large size SRAM cache memory arrays may lead to weak bits. A weak bit is a memory cell that has a relatively low current capacity as compared to a normal bit due to process/voltage/temperature (PVT) device variations. Unfortunately, the use of 8T SRAM memory cells does not overcome the effect of weak bits in conventional implementations
Accordingly, there is a need in the art for overcoming aforementioned drawbacks associated with weak bits while maximizing the benefits of 8T SRAM cells.